Flash memory has become increasingly popular in recent years. A typical flash memory comprises a memory array having a large number of flash memory cells arranged in rows, columns, and blocks. One of the most commonly known flash memories is the one-transistor flash memory, wherein individual ones of the memory cells are fabricated as a field-effect transistor having two gates: a control gate and a floating gate. The floating gate is capable of holding charges and is separated from source and drain regions contained in a substrate by a layer of thin oxide (tunneling oxide).
Each of the memory cells can be electrically charged by injecting hot electrons from the drain region or tunneling electrons from substrate and source-drain regions through the tunneling oxide layer onto the floating gate. The charges can be removed from the floating gate by tunneling the electrons to the substrate through the tunneling oxide layer during an erase operation. Thus the data in a memory cell is determined by the presence or absence of charges in the floating gate.
However, as devices in general, and flash memory cells in particular, have been scaled down in order to meet ever more demanding requirements, multiple issues may arise with respect to the performance or physical requirements of the flash memory cells. Poor or reduced cycling and data retention capabilities are two major concerns in the tunnel oxide when the tunnel oxide traps more electrons than desired during program erase operations. Such undesirable trapping of electrons makes the overall flash memory device less efficient.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.